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Analog Design Engineer - PDK Support
Location:
Santa Clara, CA
Description:
Job Description At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross functional teams to ensure design-kit leadership for customer enablement of cutting-edge technologies. You will work with customers to outline critical requirements, collaborate with Intel internal partners to define issue scope, plan execution, and innovate competitive solutions to meets customer needs.This role is to support PDK for custom template design layout/integration validation, and for analog design impact analysis and design across all Intel leading edge PDKs. You will also lead integration layout validation of custom template library cells like MFC(Multi-Finger-Capacitor), BGdiode, resistor, or clamp to make sure integration guidelines to foundry customers are all clear and correct.For impact analysis, you'll collaborate with DE teams to outline industry standard analog FOM and relevant indicators, construct, maintain and generate the simulation results, and using your deep understanding of analog design behind each indicator to interpret the gap between PDK to PDK and conducting analysis across all Intel leading advanced technology process nodes to support relevant documentation. Tasks will also include owning/maintaining training documents, user guide, and customer issue/ticket support.As a DEAS (Design Enablement Application and Support) key member, you leverage your communication skills to:- Interact with customers directly.- Apply analytical problem-solving capability to identify the key requests.- Identify root-cause issues in a teamwork environment with DE stakeholders that will support and enable customer success.# Design Enablement Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.Minimum Qualifications: Candidate must possess a BS degree with 4+ years of experience or MS degree 3+ years of experience or PhD degree with 1+ years of experience in Electrical/Computer Engineering, or related STEM fields.3+ years of experience in the following: - Prior design ownership for analog IPs (for example, PLL, AADC, ADAC, PCIE, GPIO, DDR) or equivalent designs, and knowledge for foundation circuits/blocks for these IPs.- Proficient in performing spice simulation, or hspice, or spectre, or equivalent simulators to extract simulation results.- Proficient with layout tools that would include Cadence Virtuoso, Synopsys Custom Compiler, ICV, Calibre or equivalent tools. Preferred Qualifications: - Experience or knowledge in transistor level physics and simulation. - Background or knowledge working in a team environment with layout engineers to build tight matching low capacitance and power analog blocks, resistors, capacitors, high voltage devices, etc. - Intel and/or external foundry process technology knowledge in advance nodes.- Customer-oriented and self-motivation mindset.- Verbal and written communication skills.- Ability to analyze the issues, solve problems, and bring closure. Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth. Other Locations US, Hillsboro Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Annual Salary Range for jobs which could be performed in US, California: $123,419.00-$185,123.00*Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0263412pca3lyuhf
Company:
Intel
Posted:
May 3 on ITJobsWeb
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More About this Listing: Analog Design Engineer - PDK Support
Analog Design Engineer - PDK Support is a Engineering Design Engineer Job at Intel located in Santa Clara CA. Find other listings like Analog Design Engineer - PDK Support by searching Oodle for Engineering Design Engineer Jobs.
Analog Design Engineer - PDK Support is a Engineering Design Engineer Job at Intel located in Santa Clara CA. Find other listings like Analog Design Engineer - PDK Support by searching Oodle for Engineering Design Engineer Jobs.